Assignment description 

We are looking for a Hardware Verification Engineer for our client’s team Machine Learning IP. The verification is a crucial and integral part of the hardware development and in this role you will support the design and verification of the client’s next generation IP, using the latest methodologies and technology.

As a Verification Engineer, you have opportunities to make a difference by influencing the verification strategy/methodology and contributing to the quality of the products, to develop testbenches at unit or top-level using simulation and formal methods.

Essential skills and experience:

• Strong discipline and attention to detail in ensuring effective high quality verification that minimizes bug escapes to higher levels of validation
• Coverage driven verification expertise, in high-complexity designs
• Experience in block level, top level and system level verification
• Experience in Verilog/SystemVerilog/VHDL
• Experience in the specification, creation, and debug of SystemVerilog/UVM constrained-random testbenches
• Experience in planning the verification process and making realistic effort and timescale estimates
• A hands-on self-starter, who proactively outlines and executes the steps required