Assignment Description

Our client is looking for two HW Verification Engineers to join their team Machine Learning IP in Lund.

In the company, verification is a crucial and integral part of the hardware development. In this role you will support the design and verification of the company’s next generation IP, using the latest methodologies and technology.

This role offers a hybrid work arrangement, with the flexibility to work 50% on-site and 50% remotely.

What you’ll do:

As a verification engineer, you have the opportunity to make a difference by influencing the verification strategy/methodology and contribute to the quality of the products, to develop test benches at unit or top-level using simulation and formal methods.

Qualifications:

• Strong discipline and attention to detail in ensuring effective high quality verification that minimizes bug escapes to higher levels of validation
• Coverage driven verification expertise, in high-complexity designs
• Experience in block level, top level and system level verification
• Experience in Verilog/SystemVerilog/VHDL
• Experience in the specification, creation, and debug of SystemVerilog/UVM constrained-random testbenches
• Experience in planning the verification process and making realistic effort and timescale estimates
• A hands-on self-starter, who proactively outlines and executes the steps required
• Written and spoken English

Our client is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. They are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of any characteristic.